At 53kHz and 10V the V. So why is this? Clearly I am missing or misinterpreting something? Edit: my question does not come through clearly enough, and the waveform pic seems to be confusing as it is not actual but an illustration of a waveform for a saturated transformer, similar to what I had observed.
I will grab some actual waveforms and add them to this post. To be clear about my question: Am I correct in calculating the observed V. No, you're not, I think. So, primary winding gets only 5V amplitude. Third, saturation should be prevented only while half of the clock period, because while the other half transformer magnetizes to the opposite polarity.
Hence transformer should have 0. Datasheet states for Minimum V. Maybe 15Vus stated in datasheet have a high margin and work even at 50Vus. Sign up to join this community. The best answers are voted up and rise to the top. The paper presents a simple and cost effective solution to supply high side power electronic switch gate drivers. The solution can be integrated and it is demonstrated that it can be loss free, … Expand.
View 1 excerpt, references background. In this paper, the advantages of a new resonant driver are verified thoroughly by the analytical analysis, simulation and experimental results.
A new accurate analytical loss model of the power metal … Expand. Design procedure for compact pulse transformers with rectangular pulse shape and fast rise times.
Microseconds range pulse modulators based on solid state technology often utilize a pulse transformer, since it could offer an inherent current balancing for parallel connected switches and with the … Expand.
Saturation time of transformers under dc excitation. Abstract This paper studies the saturation time of transformers under the effect of a dc voltage bias. Click here to register now. Register Log in. Forums Analog Design Power Electronics. JavaScript is disabled. For a better experience, please enable JavaScript in your browser before proceeding.
You are using an out of date browser. It may not display this or other websites correctly. You should upgrade or use an alternative browser. How to drive SCR using Pulse transformer. Thread starter chinuhark Start date Nov 24, Status Not open for further replies. I have been searching for this everywhere including the books I have but I just can't find the design procedure for the circuit used to drive an SCR using a Pulse transformer.
It is a pair of antiparallel SCRs being driven by a Pulse transformer. I have narrowed it down to the attached circuit but cannot understand how to calculate R1 and R2. I am finding it very difficult to imagine how exactly the pulse transformer works. Some circuits don't have R2 at all. Wouldn't that short circuit the secondary?
What is the max pulse width that one can use without causing saturation? Please help! Note that the Pulse transformer was bought locally and has no name or model no, let alone a datasheet. Last edited by a moderator: Jul 19, I thought this must be a standard question with a straight forward answer As noted, it is necessary that when a pulse is produced on te primary of a transformer, the power MOSFET should turn on as quickly as possible.
However, the inherent characteristics of the transformer and the effect of the leakage inductance of the power MOSFET cause a comparatively slow-rising transformer output.
In contrast, in circuit of the invention, the rise-time of the control pulse to the MOSFET is extremely short from times faster than the rise-time of the transformer thus permitting far more efficient operation of the power MOSFET.
Essentially, the rise-time of the output pulse of the pulse transformer is improved because switching of the power FET is delayed past the transition, i. While the transformer pulse is rising and during the flat-top portion thereof, the pulse is used for charging a comparatively small valued storage capacitor.
Thus, the rise of the pulse transformer sees a smaller capacitance during the rise-time of the pulse as compared to the capacitance it would have had to drive had it been coupled directly, or even through a transistor, to the large power MOSFET. In accordance with a preferred embodiment, the gate drive circuit for achieving the foregoing is comprised of a pair of diodes, a pair of series connected first and second low power FETs, the aforementioned storage capacitor and a shunt resistor connected in parallel with the storage capacitor.
The transformer pulse controls the low power FETs such that the first FET is turned on during the rise and positive portion of the pulse of the transformer which operates to keep, i. During this positive pulse the second FET is held off, and the positive pulse energy flows into, via one of the aforementioned diodes, and charges the storage capacitor to the voltage of the pulse.
In the present invention, the inductance in the series path for the gate charge and discharge of the power MOSFET is not reflected back to the primary of the pulse transformer. Also included is a pair of preferably equally sized capacitors. These capacitors are respectively connected in series with the primary and secondary windings of the transformer to equalize the flux in the core of the transformer to enable operation with large duty cycle variations.
Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.
Referring to FIG. Depending on the polarity of control signals which are applied to control inputs 14 and 16 of the CMOS switching circuit 12, a current flows in one or the other direction through the output terminals 22 and 24 of the CMOS switching circuit 12, the capacitor C1 and the primary winding PW of the transformer T1. This current is derived from the voltages which are applied to the power terminals 18 and 20 of the switching circuit By itself, the CMOS switching circuit 12 is conventional.
In accordance with FIG. The switching circuit 12 develops at its output terminals 22 and 24 a pulse control voltage whose duty cycle varies in accordance with the waveforms of the control signals which are applied to the input terminals 14 and The main purpose of the gate drive circuit 10 of FIG.
In accordance with the present invention, the pulse output at the terminals 22 and 24 of the switching circuit 12 is coupled to the gate terminal 26 of the power MOSFET 11 via the gate driving circuit This gate driving circuit 10 includes the aforementioned capacitor C1 which is connected in series with the primary winding PW of the transformer T1, forming a series circuit which is connected to the output terminals 22 and 24 of the CMOS switching circuit The transformer T1 includes one or more secondary windings, FIG.
Accordingly, positive and negative pulses applied through the output terminals 22 and 24 induce corresponding pulses at the secondary winding SW1 and SW2. On one side thereof, the secondary winding SW1 is connected to common node 28 while the second side thereof is connected to a capacitor C2 which is further connected to a circuit node In conjunction with the diode D2 which is connected between the nodes 28 and 30, a DC restorer circuit is formed by the winding SW1, the capacitor C2 and the diode D2 which assures that the voltage at the node 30 remains positive regardless of negative fluctuations of the voltage at the output terminals 22 and 24 of the CMOS switching circuit However, in response to positive voltage swings at the primary winding PW, the circuit 10 will produce positive voltage pulses at the node Diode D1 is connected with its anode at the node 30 and cathode at a further circuit node 32 and serves to conduct positive voltage pulses to the capacitor C3 to store electrical charge therein.
Both the capacitor C3 and a resistor R1 which is connected in parallel with it are disposed between the nodes 28 and The resistor R1 serves to discharge the capacitor C3 when the circuit is turned off or in the prolonged absence of positive pulses at the node As also shown in FIG. The gate driving circuit 10 operates as follows. The capacitor C3 will then be in a fully discharged state due to the presence of the resistor R1 and will comprise a low impedance for the "Miller Effect" which is induced by the power MOSFET This low impedance is attributable to the body drain diode inside the FET Q1.
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